avx512

问题 This question already has answers here : Set all bits in CPU register to 1 efficiently (2 answers) Closed 5 months ago . I need to fill zmm1 with "1" to be able quickly fill large data field in a memory in a loop. How to set zmm1 by "1" like mov rax, 0FFFFFFFFFFFFFFFFh in Intel assembly? I don't have any experience with {k1}{z} parameters. See code below. PCMPEQD zmm1, zmm1 I got an error code "invalid instruction operands" 回答1: clang++ and g++ use vpternlogd zmm0, zmm0, zmm0, 255 . I found

问题 This question already has answers here : Set all bits in CPU register to 1 efficiently (2 answers) Closed 5 months ago . I need to fill zmm1 with "1" to be able quickly fill large data field in a memory in a loop. How to set zmm1 by "1" like mov rax, 0FFFFFFFFFFFFFFFFh in Intel assembly? I don't have any experience with {k1}{z} parameters. See code below. PCMPEQD zmm1, zmm1 I got an error code "invalid instruction operands" 回答1: clang++ and g++ use vpternlogd zmm0, zmm0, zmm0, 255 . I found

问题 The Intel intrinsics guide states simply that _mm512_load_epi32 : Load[s] 512-bits (composed of 16 packed 32-bit integers) from memory into dst and that _mm512_load_si512 : Load[s] 512-bits of integer data from memory into dst What is the difference between these two? The documentation isn't clear. 回答1: There's no difference, it's just silly redundant naming. Use _mm512_load_si512 for clarity. Thanks, Intel. As usual, it's easier to understand the underlying asm for AVX512, and then you can

问题 The Intel intrinsics guide states simply that _mm512_load_epi32 : Load[s] 512-bits (composed of 16 packed 32-bit integers) from memory into dst and that _mm512_load_si512 : Load[s] 512-bits of integer data from memory into dst What is the difference between these two? The documentation isn't clear. 回答1: There's no difference, it's just silly redundant naming. Use _mm512_load_si512 for clarity. Thanks, Intel. As usual, it's easier to understand the underlying asm for AVX512, and then you can

问题 I'm trying to optimize some matrix computations and I was wondering if it was possible to detect at compile-time if SSE/SSE2/AVX/AVX2/AVX-512/AVX-128-FMA/KCVI [1] is enabled by the compiler ? Ideally for GCC and Clang, but I can manage with only one of them. I'm not sure it is possible and perhaps I will use my own macro, but I'd prefer detecting it rather and asking the user to select it. [1] "KCVI" stands for Knights Corner Vector Instruction optimizations. Libraries like FFTW detect

问题 I'm trying to create a minimal reproducer for this issue report. There seems to be some problems with AVX-512, which is shipping on the latest Apple machines with Skylake processors. According to GCC6 release notes the AVX-512 gear should be available. According to the Intel Intrinsics Guide vmovdqu64 is available with AVX-512VL and AVX-512F : $ cat test.cxx #include <cstdint> #include <immintrin.h> int main(int argc, char* argv[]) { uint64_t x[8]; __m512i y = _mm512_loadu_epi64(x); return 0;

问题 I'm missing the intrinsic _mm512_round_ps for AVX512 (it is only available for KNC). Any idea why this is not available? What would be a good workaround? apply _mm256_round_ps to upper and lower half and fuse the results? use _mm512_add_round_ps with one argument being zero? Thanks! 回答1: TL:DR: AVX512F __m512 nearest_integer = _mm512_roundscale_ps(input_vec, _MM_FROUND_TO_NEAREST_INT|_MM_FROUND_NO_EXC); related: AVX512DQ _mm512_reduce_pd or _ps will subtract the integer part (and a specified

问题 I read this article. It talked about why AVX-512 instruction: Intel’s latest processors have advanced instructions (AVX-512) that may cause the core, or maybe the rest of the CPU to run slower because of how much power they use. I think on Agner's blog also mentioned something similar (but I can't find the exact post). I wonder what other instructions supported by Skylake have the similar effect that they will lower the power to maximize the throughput later? All the v prefixed instructions

问题 I wish to perform integer arithmetic operations on Quad Word elements of the zmm 0-31 register set and preserve the carry bit resulting from those operations. It appears this is only possible if the data were worked on in the general register set. Thus I would like to copy information from one of the zmm 0-31 registers to one of the general purpose registers. After working on the 64 bit data in the general purpose register, I would like to return the data to the original zmm 0-31 register in

问题 I was looking through the instruction set in AVX-512 and noticed a set of fixup instructions. Some examples: _mm512_fixupimm_pd, _mm512_mask_fixupimm_pd, _mm512_maskz_fixupimm_pd _mm512_fixupimm_round_pd, _mm512_mask_fixupimm_round_pd, _mm512_maskz_fixupimm_round_pd What is meant here by "fixing up"? 回答1: That's a great question. Intel's answer (my bold) is here: This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that