arm

问题 I have a x86 assembly code: unsigned int oldval; __asm__ __volatile__ ( "movl $1, %0 \n" "lock xaddl %0, (%1) \n" : "=a" (oldval) : "b" (n))l; return oldval; and I want to translate it into arm assembly. Is there any prefix in arm assembly that does the same thing as "lock" here? 回答1: I don't know ARM, but from glossing over the manual, the following should approximate your atomic exchange-and-add: foo: LDREX R1, [R0] ; R0 is "n", load linked ADD R2, R1, 1 ; R2 = R1 + 1 STREX R3, R2, [R0] ;

问题 currently I am trying to build Buddhabrot for ARM architecture but I am stuck at one point when I get the following error. I hope somebody can help. libOpenCL.so uses VFP register arguments, output does not libGAL.so uses VFP register arguments, output does not here's my makefile LIBS = -lm -lOpenCL -lGAL -lGL -lGLEW -lglut -lpthread CFLAGS = -Wall -g OBJECTS = main.o environment.o input.o animate.o buddhabrot.o buddhacl.o cmodules/timer.o all: prog prog: $(OBJECTS) c++ $(CFLAGS) -o prog $

问题 Related to this other question. I am trying to run this simple C program in gem5: int main() { int a=1, b=2; int c=a+b; return c; } And it fails because gem5 doesn't have some syscalls implemented. My question is, why would a simple program like this require syscalls? This should run bare-metal without trouble. Is there a way to compile this to avoid syscalls? I am using arm-linux-gnueabi-gcc -static -DUNIX to compile it. 回答1: Without syscalls the program cannot exit. The way it works is

问题 Related to this other question. I am trying to run this simple C program in gem5: int main() { int a=1, b=2; int c=a+b; return c; } And it fails because gem5 doesn't have some syscalls implemented. My question is, why would a simple program like this require syscalls? This should run bare-metal without trouble. Is there a way to compile this to avoid syscalls? I am using arm-linux-gnueabi-gcc -static -DUNIX to compile it. 回答1: Without syscalls the program cannot exit. The way it works is

问题 I wrote a nice ARM assembler routine a few years back and it has done its job beautifully over the years on the ARM embedded systems it was designed for. Now, the time has come to port it on to non-ARM systems and I was wondering if there was tool or some sort of method to take my original ARM assembler source and get a rudimentory C file from it. I could probably do it myself in a couple of days, but it would be nice to have a starting point. Nicer still if the app or method was free :) Any

问题 How do I determine the endian mode the ARM processor is running in using only assembly language. I can easily see the Thumb/ARM state reading bit 5 of the CPSR, but I don't know if there a corresponding bit in the CPSR or elsewhere for endianness. ;silly example trying to execute ARM code when I may be in Thumb mode.... MRS R0,CPSR ANDS R0,#0x20 BNE ThumbModeIsActive B ARMModeIsActive I've got access to the ARM7TDMI data sheet, but this document does not tell me how to read the current state.

问题 The aarch64 architecture doesn't have instructions for multiple store and load, i.e. there are no equivalents of stm and ldm from armv7 arch. Instead you must use the stp and ldp instructions for store and loading pairs of registers. Accroding to the ARM reference manual: http://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf There are no multiple register LDM, STM, PUSH and POP instructions, but load-store of a non-> contiguous pair of

问题 i've a problem with the commandline command "smbclient" of samba on arm. I wrote a script to download files from a Windows Share. Here the smb-part of this script. smbclient //CNAME/SNAME -I0.0.0.0 -N -c "case_sensitive; cd folder; prompt; mget file" echo $? My problem ar the exit codes. If the file is downloaded completely, the exit code is 0 (OK) If the file cannot be downloaded, the exit code is 1 (OK) If the testmaschine loses the connection to the share due downloading a file, the exit

问题 I'm trying to understand how QEMU handles interrupts for ARM processors. I have a bare metal binary blob (ie, not linux -- just some assembly code) which was built for a ARM1176. When run in QEMU, during initialisation the code in the binary blob sets bit 13 of the CPSR indicating that the interrupt vector table is located at 0xFFFF0000 . Hooking up GDB and dumping the instructions at that address, I can indeed see the corresponding interrupt vector table. On an IRQ, it jumps to 0xFFFF0018 ,

问题 Embedded device with Cortex M3 MCU(STM32F1). It has embedded flash(64K). MCU firmware can reprogram flash sectors at runtime; this is done by Flash Memory Controller(FMC) registers (so it's not as easy as a=b). FMC gets buffer pointer and burns data to some flash sector. I want to use the last flash sector for device configuration parameters. Parameters are stored in a packed struct with arrays and contain some custom classes. Parameters can be changed at runtime (copy to RAM, change and burn