arm

Use of ARM semihosting

由 空扰寡人 提交于 2020-01-15 06:59:14
问题 I have configured a Freescale Kinetis MQX BSP to use the "iodebug:" semihosting device with an IAR IDE and J-Link debugger. The configuration "works" in that text appears in the IDE console window. The output is jerky and slow - Maybe 5 seconds to output a 16x64 block of text. During output operations the CPU appears to be stalled for long periods of time, ie. operations with strict timing requirements go off into the weeds. Is this typical performance for semihosting, or am I missing

elf file thinks its small, but its large! can not generate .bin and .hex files

由 安稳与你 提交于 2020-01-15 05:18:27
问题 I am working on migrating a project from Kail to Gcc. Makefile http://www.copypastecode.com/73860/ .ld file http://www.copypastecode.com/73856/ I have a Makefile and a platform.ld script and some .c and .h files. When i make, everything compiles and links and it looks good. arm-none-eabi-size -B Output/stm32_gps_test.elf text data bss dec hex filename 0 0 2048 2048 800 Output/stm32_gps_test.elf but when i check the generated files i see this: ls Output/ 7327274 2011-07-02 04:28 stm32_gps_test

CPU指令集架构基础学习

由 你说的曾经没有我的故事 提交于 2020-01-14 23:17:51
在最初接触C/C++的时候，我对程序编译后的指令非常着迷，循序渐进的学习了C/C++语言编译器生成汇编语言的模式。 就像是语言翻译一样，我们需要做到直接阅读x86等汇编代码，并且能够将其还原成原始的C/C++语句，这是学习逆向最有效的方法。 CPU是执行程序机器码的硬件单元，相关概念包括以下几项： **指令码：**是CPU处理的底层命令，典型的底层命令有：将数据在寄存器之间转移，操作内存，计算数值等指令，每一类CPU都有自己的指令集架构，CPU品牌有Intel,AMD,IBM和Cyrix,IDT,VIA威盛,国产龙芯等。 **汇编语言：**为了让程序员少掉头发而创造出来的，是人类可以易于读写。 **CPU寄存器：**每一种CPU都有其固定的通用寄存器（GPR），x86的CPU中有8个GPR，x64里面有16个GPR，ARM中有16个GPR，CPU寄存器就是一种存储单元，他可以无差别存储所有类型的临时变量，如果写一个程序只用到了8个32位变量，CPU自带的寄存器就可以完成任务。 需要一种将高级编程语言转成CPU可以处理的底层机器语言，这种程序就是编译器（Compiler）。 0x01 指令集架构 x86的指令集架构中，opcode（汇编指令对应的机器码）长度是不同的。 ARM属于RISC（精简指令集）架构 CPU，这种指令集在设计之初就力图保持各个opcode长度一致，最初的时候

How to properly initialize I2C stm32?

由 ╄→гoц情女王★ 提交于 2020-01-14 15:49:10
问题 I want to get data from ADXL345 accelerometer,but seems that I incorrectly connect it. SCL- PC6(with 10k resistor) SDA- PC7(with 10k resistor) SDO- GND CS - VCC GND - GND 3.3v - VCC Here is my code to initalize: void I2CG_Init(void) { GPIO_InitTypeDef GPIO_InitStructure; I2C_InitTypeDef I2C_InitStructure; RCC_AHBPeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); RCC_AHBPeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); // I2CG clock enable RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2CG, ENABLE); RCC

Erratic cycle counts on ARM Cortex-M0

由 ぃ、小莉子 提交于 2020-01-14 14:32:17
问题 [A lot of text incoming, since I want to detail my question as best as I can.] I'm in the process of optimizing hand-written ARM assembly code for a Cortex-M0. The board I'm using is the STMicro STM32F0Discovery, which has an STM32F051R8 controller. The controller is running at 48 MHz. Unfortunately, I'm getting some pretty strange cycle counts when doing optimizations. For example, adding a single nop into a loop in my code should add 2 cycles in total (looped 2 times). However, doing so

Erratic cycle counts on ARM Cortex-M0

由 馋奶兔 提交于 2020-01-14 14:32:07
问题 [A lot of text incoming, since I want to detail my question as best as I can.] I'm in the process of optimizing hand-written ARM assembly code for a Cortex-M0. The board I'm using is the STMicro STM32F0Discovery, which has an STM32F051R8 controller. The controller is running at 48 MHz. Unfortunately, I'm getting some pretty strange cycle counts when doing optimizations. For example, adding a single nop into a loop in my code should add 2 cycles in total (looped 2 times). However, doing so

how can I get the ARM MULL instruction to produce its output in a uint64_t in gcc?

由 谁都会走 提交于 2020-01-14 11:53:33
问题 I would like to introduce some assembly code into a c99 codebase. I want to use the UMULL instruction from the ARM CPU to multiply 2 uint32_t and get the result immediately into a uint64_t. Now a uint64_t needs 2 registers, so how do I specify the output and the constraints of the asm block? 回答1: Good question! The following code outputs what you want using GCC -O or higher without resorting to assembler: uint32_t a, b; uint64_t c; ... c = (uint64_t)a * (uint64_t)b; or if you feel you must

Is there a way to detect VFP/NEON/Thumb/… on iOS at runtime?

由 主宰稳场 提交于 2020-01-14 10:29:08
问题 So it's fairly easy to figure out what kind of CPU an iOS device runs by querying sysctlbyname("hw.cpusubtype", ...) , but there seems to be no obvious way to figure out what features the CPU actually has (think VFP, NEON, Thumb, ...). Can someone think of a way to do this? Basically, what I need is something similar to getauxval(AT_HWCAP) on Linux/Android, which returns a bit mask of features supported by the CPU. A few things to note: The information must be retrieved at runtime from the OS

ARMv8 - Running legacy 32 bit Applications on 64 bit OS

由 笑着哭i 提交于 2020-01-14 09:49:27
问题 Going thru the ARMv8 manual, I have the following questions to help understand the big picture. Can legacy 32 bit app. (ARMv7 or earlier) run as is on the ARMv8 OS? If the legacy applications need to be rebuilt for ARMv8 and assuming that I rebuild the application as 32 bit (Aarch32), does this need 32 bit OS underlying support? (It is interesting to know how the addressing mechanism works here.) Please provide references wherever possible. PS: I am targeting Linux OS with Aarch64 support (3

ARMv8 - Running legacy 32 bit Applications on 64 bit OS

由 余生长醉 提交于 2020-01-14 09:49:12
问题 Going thru the ARMv8 manual, I have the following questions to help understand the big picture. Can legacy 32 bit app. (ARMv7 or earlier) run as is on the ARMv8 OS? If the legacy applications need to be rebuilt for ARMv8 and assuming that I rebuild the application as 32 bit (Aarch32), does this need 32 bit OS underlying support? (It is interesting to know how the addressing mechanism works here.) Please provide references wherever possible. PS: I am targeting Linux OS with Aarch64 support (3
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