How to create a string from a pre-processor macro

Question

I have a preprocessor macro that represents a hierarchical path into my design.

Example:

`define HPATH top.chip.block

I need to constru

Answer 1

I think this is what you're looking for.

`define HPATH `"top.chip.block`"
string hpath = `HPATH;

As toolic pointed out, the escape sequence %m will give you the current hierarchy when used in a $display statement so that may be a better option.

Answer 2

It's not possible to use a `define macro within a string literal. According to the SystemVerilog LRM:

Macro substitution and argument substitution shall not occur within string literals.

However a string literal can be constructed by using a macro that takes an argument and including the quotes in the macro by using ``"`.

Again, from the LRM:

An `" overrides the usual lexical meaning of " and indicates that the expansion shall include the quotation mark, substitution of actual arguments, and expansions of embedded macros. This allows string literals to be constructed from macro arguments.

So this works:

`define STRINGIFY(x) `"x`"
`define HPATH top.chip.block
string hpath = `STRINGIFY(`HPATH);
$display(hpath);                       // Output: "top.chip.block"

The example code can be run here: http://www.edaplayground.com/s/4/879

Answer 3

I know this is an old thread, but I thought I'd share our solution. The use of the $sformatf allows additional information to be added if needed.

`define STRINGIFY(DEFINE) $sformatf("%0s", `"DEFINE`")