Difference between “parameter” and “localparam”

Question

I\'m writing a project with Verilog and want to use parameter to define some parameter in my module. But when I read in some source code, localparam so

Answer 1

Generally, the idea behind the localparam (added to the Verilog-2001 standard) is to protect value of localparam from accidental or incorrect redefinition by an end-user (unlike a parameter value, this value can't be modified by parameter redefinition or by a defparam statement).

Based on IEEE 1364-2005 (ch. 4.10.2):

Verilog HDL local parameters are identical to parameters except that they cannot directly be modified by defparam statements or module instance parameter value assignments. Local parameters can be assigned constant expressions containing parameters, which can be modified with defparam statements or module instance parameter value assignments.

Additionally, in SystemVerilog (IEEE 1800-2012 (ch. 6.20.4)):

Unlike nonlocal parameters, local parameters can be declared in a generate block, package, class body, or compilation-unit scope. In these contexts, the parameter keyword shall be a synonym for the localparam keyword.

Local parameters may be declared in a module’s parameter_port_list. Any parameter declaration appearing in such a list between a localparam keyword and the next parameter keyword (or the end of the list, if there is no next parameter keyword) shall be a local parameter. Any other parameter declaration in such a list shall be a nonlocal parameter that may be overridden.

If you want to learn more about this topic, I'd recommend you Clifford E. Cummings paper "New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)".

Answer 2

Minimal example

Here is an example of what Qiu mentioned.

In a RAM, the memory size is a function of the word and address sizes.

So if the parent module specifies word and address size, it should not be able to specify the memory size as well.

module myram #(
    parameter WORD_SIZE = 1,
    parameter ADDR_SIZE = 1
) (
    input wire [ADDR_SIZE-1:0] addr,
    inout wire [WORD_SIZE-1:0] data,
    // ...
);
    localparam MEM_SIZE = WORD_SIZE * (1 << ADDR_SIZE);
    // Use MEM_SIZE several times in block.
...

And on parent module, this is fine:

module myram_tb;
    myram #(
        .ADDR_SIZE(2),
        .WORD_SIZE(2)
    ) top (
        /* wires */
    )

but this should be an error:

module myram_tb;
    myram #(
        .ADDR_SIZE(2),
        .WORD_SIZE(2),
        .MEM_SIZE(2)
    ) top (
        /* wires */
    )

iverilog doesn't fail, and I believe that this is a bug: https://github.com/steveicarus/iverilog/issues/157

Incisive gives an error as expected.