Memory mapped IO - how is it done?

Question

I\'ve read about the difference between port mapped IO and memory mapped IO, but I can\'t figure out how memory mapped Io is implemented in modern operating systems (windows or

Answer 1

The following statement in your question is wrong:

What I know is that a part of the physical memory is reserved to communicate with the hardware

A part of the physical memory is not reserved for communication with the hardware. A part of the physical address space, to which the physical memory and memory mapped IO are mapped, is. This memory layout is permanent, but user programs do not see it directly - instead, they run into their own virtual address space to which the kernel can decide to map, wherever it wants, physical memory and IO ranges.

You may want to read the following articles which I believe contain answers to most of your questions:

• http://duartes.org/gustavo/blog/post/motherboard-chipsets-memory-map
• http://duartes.org/gustavo/blog/post/memory-translation-and-segmentation
• http://duartes.org/gustavo/blog/post/how-the-kernel-manages-your-memory

Answer 2

http://en.wikipedia.org/wiki/Memory-mapped_I/O

http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/IO/mapped.html

Essentially it is just a form of accessing the data, as if you are saving / reading from the memory. But the hardware will snoop on the address bus, and when it sees the address targetting for him, it will just receive the data on the data bus.

Answer 3

Are you asking about Memory mapped files, or memory mapped port-IO?

Memory mapped files are done by paging out the pages and intercepting page-faults to those addresses. This is all done by the OS by negotiation between the file-system manager and the page-fault handler.

Memory mapped port-IO is done at the CPU level by overloading address lines as port-IO lines which allow writes to memory to be translated onto the QPI bus lines as port-IO. This is all done by the processor interacting with the motherboard. The only other thing that the OS needs to do is to tell the MMU not to coalese reads and writes through the PAE must-writethrough and no-cache bits.