wait statement must contain condition clause with UNTIL keyword

Question

The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : \"wait statement must contain condition clause with UNTIL k

Answer 1

You get this error because you have set your testbench as the top-level entity in Quartus-II. The top-level entity must remain the component case_ex, and this component must contain synthesizable code.

To simulate your testbench, you must configure a testbench. Just klick on the plus-sign before "RTL Simulation" and then "Edit Settings". (Names may differ with Quartus version).