VHDL syntaxe error near if

Question

I\'m a trying to find out the problem with this simple VHDL code. I\'ll be grateful if someone could help me. PS: I tried the code without the conditional block and it w

Answer 1

An if statement is a sequential statement, and from your usage should either be in a process statement or you should instead use a concurrent signal assignment statement. It hardly seems complex enough for a process statement.

Concurrent assignment statement:

 Cout <= A(3) and B(3);

Note that concurrent assignment statement using an expression as the value in it's signal assignment can pass values other than '0' or '1'.

A different style of concurrent signal assignment statement could pass only binary representing enumeration values:

Cout <= '1'  when A(3) = '1' and B(3) = '1' else '0';

(Your if statement also appears to infer a latch and could be optimized as a constant '1').

Note also that your original if nested statements could be expressed with a BOOLEAN and which is a short-circuit operator taking the place of Ada's if expression and then .... Without one or more intervening statements following an if statement (including it's end if) there is no reason to nest if statements with different expressions. The short-circuit operator would only evaluate the subsequent expression if the first expression evaluated true.

The form would be along the lines of

if A(3) = '1' and B(3) = '1' then
    Cout <= '1';
end if;

And could still only be used where a sequential statement is appropriate.

Note that std_logic requires enumeration values ('U', 'X', '0', '1',...) while 1 is a numeric value and would result in errors.

Answer 2

Besides David's (correct) answer, note that if you are trying to make a 4-bit adder with Cout as the carry output, that process will not give the correct value. Consider A = "1111" and B = "0001". A(3) is '1' but B(3) is not, and the result is S = "0000" and Cout should be '1' but is '0'.