What is multiple constant driver error in VHDL

Question

I am developing a VHDL program for flash interface. While compiling my program I got this error.

(clickable)

As you can see in the picture, two signal

Answer 1

Are you doing something like this?

ENTITY test IS
  PORT ( sig1, sig3 : IN BIT;
         sig2 : OUT BIT);
END test;
---------------------------
ARCHITECTURE test_arch of test is
BEGIN
  PROCESS(sig1)
  BEGIN
    sig2 <= '0';
  END process;

  PROCESS(sig3)
  BEGIN
    sig2 <= '1';
  END process;
END test_arch;

Let us test this code:

ghdl -a test.vhd
ghdl -e test
ghdl -r test

we get this error:

sig2
./test:error: several sources for unresolved signal
for signal: .test(test_arch).ghdl: compilation error

This is similar to the one you have posted above and it's come up because my code assigns a value to sig2 in two different processes. How could this be implemented into a circuit?

Maybe there is a workaround, I have not provided a solution to your problem since I don't know how your code looks like.

Answer 2

A Google search for "Error (10028) altera" returns this Altera Quartus II help as first hit, saying:

Can't resolve multiple constant drivers for net "<name>" at <location> (ID: 10028)

CAUSE:
In the current design, multiple constant (non-tri-state) drivers are contending for the specified net, which was created by Quartus II Integrated Synthesis to represent one or more signals. This condition usually occurs when a Verilog Design File (.v) or VHDL Design File (.vhd) contains multiple concurrent assignments to the same signal. Quartus II Integrated Synthesis attempted to resolve the electrically equivalent assignments, but cannot resolve the contending assignments into a single equivalent driver.

The message(s) immediately below this message indicate the constant drivers to the net that conflict with the net's first constant driver.

ACTION: Check the design for multiple concurrent assignments to the same signal.

The case is that in synthesis there can only be one driver for each signal, where in simulation there can be multiple for resolved signals, so you may see that the design passes compile in simulation, but doesn't in synthesis.

So look for multiple drives for flash_oe.