GNU make - transform every prerequisite into target (implicitly)

Question

I have another make-like tool that produces an XML as an artifact after parsing my makefile which I\'ll then further process with Python.

It\'d simplify thi

Answer 1

Try generating static pattern rules for the header files. See one of the answers to Make ignoring Prerequisite that doesn't exist.

Static pattern rules only apply to an explicit list of target files like this:

$(OBJECTS): %.o: %.c
    *recipe here*

where the variable OBJECTS is defined earlier in the makefile to be a list of target files (separated by spaces), for example:

OBJECTS := src/fileA.c src/fileB.c src/fileC.c

Note that you can use the various make utility functions to build that list of target files. For example, $(wildcard pattern), $(addsuffix), etc.

You should also ensure that the recipe "touches" the header file to change the timestamp.

I've found that using static pattern rules instead of pattern rules fixes problems where make doesn’t build prerequisites that don’t exist, or deletes files that you want.

---

Here is an example of using wildcard to copy files from one directory to another.

# Copy images to build/images
img_files := $(wildcard src/images/*.png src/images/*.gif src/images/*.jpg \
src/images/*.mp3)

build_images := $(subst src/,$(BUILD_DIR)/,$(img_files))
$(build_images): $(BUILD_DIR)/images/% : src/images/%
    mkdir -p $(dir $@)
    cp -v -a $< $@

There are other make functions like addprefix that could be used to generate a more complex file specification.

Answer 2

This may take a few iterations. Try:

%.h: null
    @echo header xyz = $@

%: null
    @echo other xyz= $@

null:
    @: