In simulation, a Verilog wire behaves like a piece of metal, a track, a wire, whilst a Verilog reg is a variable, it is storage*.
The difference between them in simulation can be illustrated by showing what happens if I assign to them from more than one place. If I assign to a wire from more than one place, the simulation will behave exactly as if I had shorted those two wires together. So,
wire w;
assign w = 1'b1;
assign w = 1'b0;
initial
$display("w= %b", w);
will display x. The value of w will be x because one assign is driving 1'b1 and the other 1'b0 and so this will resolve to an x. In this way it is modelling the behavoiur of real hardware, where x represents an unknown value (the value of a real piece of wire drive high by one driver and low by another will really be unknown).
If I assign to a reg - a variable - from more than one place, I will get different behaviour. Instead of resolving to an x, the reg will just take whatever value is assigned last. So,
reg r;
initial
r = 1'b1;
initial
r = 1'b0;
initial
#1 $display("r= %b", r);
will display either 1 or 0 depending on which initial block is executed last (something that is not deterministic).
Notice, that the reg is driven from initial blocks. A reg has to be driven from an initial or an always block (so-called procedural code). Assuming you are writing Verilog, not System Verilog, you cannot assign to a reg from an assign statement nor from the output of an instantiated module. So, if you want to assign to something from procedural code, you have to use a reg; if you want to assign to something from an assign statement or the output of an instantiated module, it has to be a wire. And, therefore it follows that whether you define an output as a reg or a wire depends entirely on where you're assigning to it. If you're assigning to it from an always block, it needs to be a reg; if you're assigning to it from an assign statement or the output of an instantiated module, it needs to be a wire.
That is the difference in the behaviour of a reg and a wire in simulation. Your synthesiser, will interpret a reg differently. If you assign to a reg from more than one always block (you can't synthesise initial blocks), then you logic synthesiser will synthesise two pieces of hardware driving the same piece of metal, track, wire, whatever - something you probably don't want.
*That does not mean a reg will necessarily become storage (ie a flip-flop) when synthesised. Whether, a `reg becomes a flip-flop or combinational logic depends on whether it is assigned in a sequential- or combinational-style always block.
