how many processes i need to monitor two signals?

Question

I am a vhdl begginner, and in need of help for my problem. I have 2 signals that i need to monitor. One is CHECK and the other OK. Every time i ask for a CHECK, I should get

Answer 1

I'd say making a single-process state machine is the best way to start. It saves some potential problems with latches being formed, and stops you jumping all over the place trying to see what is going on in each state (for which you have to look in two or even three separate places). But I'm not sure you need a full blown FSM!

Your original code doesn't look too bad. A quick comment on it:

You can add integers to unsigned vectors, so you don't have to do this:

lost_count := lost_count + to_unsigned (1,3);

you can just do:

lost_count := lost_count + 1;

I'd make lost_counter an integer too, rather than an unsigned vector, as you are not requiring it to wrap around, nor wanting values greater than 2**31, nor do you want direct access to the bits. Therefore an integer is a win all round.

It looks like you want to find 6 consecutive 0 bits - the following code is how I would do it - it will go inside the clocked process (of your first try):

if ok = '0' then
    lost_counter := lost_counter + 1;
else
    lost_counter := 0;
end if;
trip <= '0';
if lost_counter = 6 then
    trip <= '1';
    lost_counter := 0;
end if;  

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Update regarding clocks...

Yes, it's pretty much mandatory to have a clock, so the rising_edge is done on the clock, and then you use that transition to sample all the signals you are interested in. There are other ways of doing it, but they are only for very advanced special cases. The method of using a single clock for every process is called "synchronous design" and it is so widely used that all the tools really expect it of you.

In order to find the rising edge of your CHECK signal, you will have to look at it (sample it) on the rising edge of your clock, store the value, and then compare it with the next value when you get the next clock edge. If the last one was a zero and the current one is a one, you know it has "risen" between the clock edges, and you can do whatever you like at that point. See also my answer here on this subject:

https://stackoverflow.com/a/20472791/106092

Answer 2

This is a pretty standard state machine, and most designers will use from one to three processes for a state machine. If you are just starting out then using three processes may make things easier for you. The processes would be:

1. Using the current state of the counter and the input signals, decide what the next state should be.
2. Using the current state of the counter and the input signals, decide what the values of all output signals should be.
3. At the desired clock edge, load the next state of the counter (from 1.) into the counter.

Note that the first two processes are purely combinational logic while the third is a clocked, sequential process.