Verilog Loop Condition

Question

I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2

Answer 1

I don't think you want to use a while loop there. How about:

   always@ (posedge CLOCK_50 or negedge reset_n) begin
           if(!reset_n)
               count <= 0;
           else if (enable)
               count <= count + 1;
    end

I also added non-blocking assignments <=, which are more appropriate for synchronous logic.

Answer 2

The block will trigger every time there is a positive edge of the clock. Where you had a while loop does not mean anything in hardware, it would still need a clock to drive the flip flops.

While loops can be used in testbeches to drive stimulus

integer x;
initial begin
  x = 0;
  while (x<1000) begin
    data_in = 2**x ; //or stimulus read from file etc ...
    x=x+1;
  end
end

I find for loops or repeat to be of more use though:

integer x;
initial begin
  for (x=0; x<1000; x=x+1) begin
    data_in = 2**x ; //or stimulus read from file etc ...
  end
end

initial begin
  repeat(1000) begin
    data_in = 'z; //stimulus read from file etc (no loop variable)...
  end
end

NB: personally I would also add begin end to every thing to avoid adding extra lines later and wondering why they always or never get executed, especially while new to the language. It also has the added benefit of making the indenting look a little nicer.

always@ (posedge CLOCK_50 or negedge reset_n) begin
  if(!reset_n) begin
    count <= 'b0;
  end
  else if (enable) begin
    count <= count + 1;
  end
end

Answer 3

Title

Error (10119): Verilog HDL Loop Statement error at : loop with non-constant loop condition must terminate within iterations Description

This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.

Workaround / Fix

To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:

set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300