Reading OUT ports for debugging

Question

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := \'0\';
    DIN                    


        

Answer 1

Use BUFFER instead of out. Then you can read without the intermediate signal used in Charles' solution.

Answer 2

You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

or

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);

Answer 3

You have good answers already for older tools - but if you use some tool which supports VHDL-2008, you are allowed to read output ports directly. You may need to enable this with a command line option.

If your tools don't support it, whinge at the supplier until they do!