How to NOT use while() loops in verilog (for synthesis)?

Question

I\'ve gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I\'ve taken this habit over to cod

Answer 1

Synthesis tools vary but generally a loop can be synthesized so long as the number of iterations is known a to the synthesis tool. So,

for ( i = 0; i < 10; i = i + 1 )

is OK because the tool knows there are 10 loop iterations. But

reg [10:0] r;
for ( i = 0; i < r; i = i + 1 )

is not OK because r is a variable r's value is unknown at synthesis time.

Think of loops in RTL code as creating a known fixed number of copies of a piece of logic.

Answer 2

You need to have a clock to control it to start.

always @(posedge clk or negedge rst_n)
  if (!rst_n)
     num <= 32'b0; // or whatever your width is.
  else
     if (num < test_number)
       num <= num + 1'b1;

Answer 3

If your synthesis tool does not support while or for loops, then don't use a loop. Just expand your code out.

wire [1:0] addr;
reg  [3:0] wren;

always @(posedge clk) begin
    wren[0] <= (addr == 2'd0);
    wren[1] <= (addr == 2'd1);
    wren[2] <= (addr == 2'd2);
    wren[3] <= (addr == 2'd3);
end

I am unfamiliar with XST, but some synthesis tools do support loops (Synopsys, for example).