calculate (and validate) ethernet FCS (crc32) in vhdl

Question

I\'m using the Spartan 3E Starter Kit and I\'m trying to receive Ethernet frames on it via a 100 MBit link.

For those who don\'t know, the board features a PHY chip, exp

Answer 1

The generator you used may not be pre-processing and post-processing the data. If that generator takes a string of zeros and produces a zero crc, then that's the problem. A string of zeros should not produce zero. (What it produces depends on the number of zeros.)

The processing for the Ethernet crc is to invert the crc, then apply the crc algorithm, then invert the crc again.

Answer 2

I started working on an ethernet MAC a while back, and although I never got round to finishing it I do have a working CRC generator that you can use here:

CRC.vhd

Its based on a Xilinx App note on the IEEE 802.3 CRC, which you can find here.

The CRC is instantiated in the ethernet receieve component, if you look at the ETH_RECEIVE_SM process you can see how the FCS is loaded into the checker.

Hopefully you can spot your mistake by comparing with my code.

Edit:

I took the sample ethernet frame from fpga4fun and passed it through the CRC checker, see the simulation screenshot below (right click, copy URL and view in a new browser tab for full resolution):

You can see the residual C704DD7B at the end there, try doing the same with your own CRC checker and see what you get.