VHDL: truth table in ieee std_logic library

Question

I looked into how IEEE defines its libraries. When I opened up stdlogic library, I saw a few truth tables that are defined as constant. I have no idea how the truth tables funct

Answer 1

The AND table replete with declarations you show is a two dimensional array, indexed by std_ulogic (enumerated) values. An AND function has a left and right argument (l and r), use to index a result in the table.

The table is shown as a 2D array to make it user readable, the intersection of a column comment enumerated value index and row comment enumerated value index indicating the result of a logical AND operation.

Resolution functions are a bit more complex and involve advanced reading either from the standard or various explanatory texts.

A resolution function is used to 'resolve' multiple drivers on a signal. The various driver values are organized as a vector with the length equal to the number of drivers, where after the first driver value being 'resolved' against a default driver (in this case see the package body of std_logic_1164, the default value for result is 'Z'), each successive driver is resolved by resolution table look up against the accumulated result.

The purpose is to determine the 'resolved' signal value of a signal having multiple drivers, in this case using the MVL9 (multi level logic with 9 levels) adopted as an IEEE Standard (IEEE Std 1164, now part of VHDL standard. It's part of the language (and not as Guy Sirton indicates solely an electrical engineering issue).

Setting up resolution occurs during elaboration it's a function of simulation.

Any two concurrent statements driving the same signal require resolution. Resolution occurs even with only one driver (against that default 'Z'). If you don't use resolved types you'll get an error message. If you use resolved types you'll get a resolution value and won't be protected against connecting multiple drivers to the same signal when perhaps you shouldn't be doing so.

addendum

One more question. To navigate through a 2D array, I thought we use array index. Like (1,2) = row 1, column 2. use how does and_table(U,1) matches up Row 1, Column 4 or Column 1 row 4? – Hong Pan 1 hour ago

The question and answer format isn't set up for 'One more question'.

The indexes are type std_ulogic, not numerical types. An enumerated type has a positional value that can be expressed as a numerical type. For std_ulogic enumeration values, the first value is 'U' the next is 'X',... on to '-'. To find a std_ulogic positional value you could use the 'POS attribute where std_ulogic'POS(l) will return an index position value for l. You can convert a universal integer number representing a positional value to a std_ulogic value by using the 'VAL attribute.

The index values l and r are used by convention to signify left and right operands to predefined binary operators. l AND r provides the two indexes as l and r.

FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
    RETURN (and_table(l, r));
END "and";

You're not allowed to specify a predefined operator with an interface list - AND(l,r). l is the second dimension, specifying rows while r specifies columns. And it doesn't matter in these cases, the tables work the same switching the two indexes.

Note the return value is a subtype (UX01) of std_ulogic and only those four values are found in the table.

And all of this can be discerned by the knowledgeable VHDL user from the the information you provided in your example. It speaks to the need for a a good text on the language or access to the standard (IEEE Std 1076-2008), wherein all answers can be found.