VHDL synthesis warning FF/Latch has a constant value of 0

Question

I\'m trying out some code that essentially involves using an FPGA and reading values from a temperature sensor.

The code is below:

library IEEE;
use          


        

Answer 1

I guess, this warning (FF/Latch) occurs when we forget to assign some value for some signals (or even maybe we think that it is not necessary to assign some value), especially when there are some conditions like if-else. It is expected that for all conditions we assign a value. So, it makes our code neatly and also long to repeat some assignment in every condition, but we can set an initial value for all those signals (which the FF/Latch warning refers to them) exactly after begin of a process and before if rising-edge. For example, in STATE_Transition procecc, between begin and if rising_edge, you should write write_temp <= (others=>'0').

Answer 2

dear same problem i am facing same problem running my code on fir, i have run your code it synthesis but due to warning it show's undefined values of your input and clk, don't assign 0 value, try to put different value like write_temp 7 to 1. i am not full expert of vhdl but when i make this change similar way i get over these warning, hope this work for you also.

Answer 3

Nothing is wrong here. The warning says that write_temp_0 is always 0 - that is, the warning only applies to bit 0 of write_temp, not the other 7 bits.

This is to be expected, as you never set bit 0 of write_temp to be anything but 0. The synthesizer picks up on this, and optimizes it by simply trimming it to be a constant 0 instead of being connected to logic.

So try out the code and see if it works - if it doesn't, it's probably due to other reasons.

Also, when writing and verifying code like this, the simulator is a fantastic tool - it'll allow you to locate logic errors in your code very easily. So no reason not to get to know how to use it.