signed to std_logic_vector, slice results

后端 未结 2 1173
佛祖请我去吃肉
佛祖请我去吃肉 2021-01-18 11:53

I need to take the absolute value of a result and I am only interested in the most significant bits. This is what I have done:

data_ram_h <= std_logic_vec         


        
相关标签:
2条回答
  • 2021-01-18 12:00

    Finally I solved my doubt. Even std_logic_vector is a function, so I need 3 variables to slice the result without errors. Here what I did:

        h_tmp <= abs(signed(resize(r4(calc_cnt - 2), data_ram_h'length) + r4(calc_cnt - 1) +
                        r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) -
                        r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) -
                        r2(calc_cnt + 1) - r2(calc_cnt + 2)));
        h_tmp_vec <= std_logic_vector(h_tmp);
        data_ram_h <= h_tmp_vec(11 downto 4);
    

    With the following definitions:

    signal h_tmp: signed (11 downto 0);
    signal h_tmp_vec: std_logic_vector (11 downto 0);
    signal data_ram_h: std_logic_vector(7 downto 0);
    

    Thanks Paebbels for your comment :)

    If someone has a better way to solve it, please post it!

    0 讨论(0)
  • 2021-01-18 12:18

    A type conversion is a basic operation that happens to require parentheses around it's operand expression. And there's the rub, it's use is not a function call, so it can't be used as a prefix for a slice name.

    A prefix for a slice name is either a function_call or a name. (IEEE Std 1076-2008, 5 Types, 5.1 General, explicit type conversion, 8 Names, 8.1 General, 8.5 Slice names).

    If it was a function call you could slice the result.

    On the other hand you can slice `"abs", so slice that and then do the type conversion:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    
    entity slice is
    end entity;
    
    architecture foo of slice is
        signal h_tmp: signed (11 downto 0);
        signal h_tmp_vec: std_logic_vector (11 downto 0);
        signal data_ram_h: std_logic_vector(7 downto 0);
        signal calc_cnt:     integer := 3;
        type r_array is array (0 to 15) of unsigned(15 downto 0);
        signal r2, r4: r_array := (others => (others => '0'));
    begin
    
    
        data_ram_h<= std_logic_vector (
                         "abs"(signed(resize(r4(calc_cnt - 2), data_ram_h'length) + r4(calc_cnt - 1) +
                          r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) -
                          r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) -
                          r2(calc_cnt + 1) - r2(calc_cnt + 2)))(11 downto 4)
                          );
    
    end architecture;
    

    Using abs as a function call requires you use it's declared name which is "abs".

    I'm just guessing at some declarations here, so I can't guarantee this works in your code. The above example does analyze, elaborate and run which says the subtype ranges are compatible.

    0 讨论(0)
提交回复
热议问题