In gnu make, can the prerequisites in a static pattern rule have different suffixes

Question

Our make file compiles .c source files with a static pattern rule like this:

OBJECTS = foo.o bar.o baz.o

$(OBJECTS): %.o: %.c
    $(CC) $< $(C_OPTIONS) -         


        

Answer 1

We can add this either-or behavior to the list of things Make should be able to do easily, but isn't. Here's a way to do it, using "eval" to create a seperate rule for each object.

define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef

OBJECTS = foo.o bar.o baz.o

$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))

$(OBJECTS):
    $(CC) $< $(C_OPTIONS) -c -o $@ 

Note that this depends on the source files already existing before you run Make (foo.c or foo.m, but not both). If you're generating those sources in the same step, this won't work.

Here's a less clever, more robust method.

CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)

$(CPP_OBJECTS): %.o: %.c 

$(OBJECTIVE_OBJECTS): %.o: %.m 

$(OBJECTS):
    $(CC) $< $(C_OPTIONS) -c -o $@ 

EDIT: corrected OBJECTS assignment, thanks to Jonathan Leffler.

Answer 2

The call to the same compiler is just a happy occasion. Normally you do not compile objective-c code with $(CC). That just feels strange.

But since you go in a harsh way, I won't post do-it-right solution, where you separate objective-C targets from C targets into two different $(OBJECTS)-like variables and make two rules (which you should really do). Too boring. Instead, take a hack!

OBJC_FILES:=$(subst $(wildcard *.m))

real_name = `(test -h $(1) && readlink $(1) ) || echo $(1)`

$(OBJECTS): %.o: %.c
  $(GCC) $< $(C_OPTIONS) -c -o $(call real_name,$@)

$(OBJC_FILES): %.c: %.m
  ln -s $< $@

And God help those who maintains it!

Btw, this obviously won't work if your m-files are generated.

Answer 3

Not really just copy to

$(OBJECTS): %.o: %.m
  $(CC) $< $(C_OPTIONS) -c -o $@