Using a make file to compile files in separate directories

Question

OK, I have never been able to grasp make, and makefiles. I\'ve tried reading through the manpages with no luck. So I have come here :L

I have a bunch of files that a

Answer 1

Let's take this in stages:

all: $(SOURCES) link

You don't have to build the sources, so let's leave that out. And what you really want to build is kern/kernel, so let's use that instead of the abstract "link:

all: kern/kernel

kern/kernel:
    ld $(LDFLAGS) -o kernel $(SOURCES)

But you want to link the object files, not the source files, and produce kernel in kern/, not in the parent directory (where I assume you will be running make):

kern/kernel: $(OBJECTS)
    ld $(LDFLAGS) -o $@ $^

And what are the objects? Well, I presume the sources are the .s files, and the objects have the same names with a different suffix, and in a different location:

SOURCES=boot.s main.s monitor.s common.s descriptor_tables.s isr.s interrupt.s gdt.s timer.s kheap.s paging.s

OBJECTS=$(patsubst %.s,Obj/%.o,$(SOURCES))

And this is how you make an object:

$(OBJECTS): Obj/%.o : %.s
    nasm $(ASFLAGS) $<

vpath %.s Src

(That last line is so that Make will know where to find the sources.)

The flags look good. And here's clean:

.PHONY: clean
clean:
    -rm -f Obj/*.o kern/kernel

You're trying to do a lot at once, so this probably won't work on the first try. Give it a whirl and let us know the result.