Make ignores generated dependencies

Question

I\'m trying to write a Makefile for my project that automatically generates the dependencies between my source files. The Makefile is as follows:

CC = g++

C         


        

Answer 1

People often have such rules for dependency generation, but they are really unnecessary.

The first time a project is built no dependencies are necessary since it builds all sources anyway. It is only the subsequent builds that require the dependencies from the previous build to detect what needs to be rebuilt.

The dependencies are just a by-product of compilation.

---

The generated dependencies contain paths to corresponding .o files. Since .o output paths were not specified when generating dependencies, those paths are incorrect.

The following solution puts .d files along with corresponding .o files and those .d files contain the correct paths to .o. It also does compilation and dependencies in one pass.

Fixes:

Remove these lines:

$(DEPS): $(DEPDIR)/%.d : $(SRCDIR)/%.cpp
    $(CC) $(CFLAGS) -MM $< -MF $@
-include $(DEPS)

Update these lines:

DEPS = $(OBJS:%.o=%.d)
$(OBJDIR)/%.o: $(SRCDIR)/%.cpp 
    $(CC) -c $(CFLAGS) -MD -MP -o $@ $< 

Add these lines at the bottom:

ifneq ($(MAKECMDGOALS),clean)
-include $(DEPS)
endif