How SCI - System Control Interrupt vector is defined?

Question

According to the ACPI spec, The FADT (Fixed ACPI Description Table) table contains a field that reports the SCI interrupt number to OS. The

Answer 1

Throughout the ACPI specifications every notification event that uses the interrupting mechanism gets associated with a Global System Interrupt (GSI).
GSIs are briefly described in section 5.2.13 Global System Interrupts of the 6.1 ACPI specifications linked previously¹.

Global System Interrupts can be thought of as ACPI Plug and Play IRQ numbers.
They are used to virtualize interrupts in tables and in ASL methods that perform resource allocation of interrupts.

The specifications use the term system vector to denote the number of the GSI.
For example, the GSI number 9 has system vector number 9.
This is admittedly confusing as the term "vector" can be mistaken for the term "vector" in "interrupt vector" as used in Intel manuals.

To understand GSIs one must have a minimum understanding or IRQs.
The two standard interrupt controllers on an x86 system are

1. The 8259A PIC ^{[datasheet] [OSDev wiki]}
   There are always two PICs, at standard IO addresses, each with eight input pins (IR 0-7).
   One PIC is the master and handles IRQ 0-7.
   The other is the slave and handles IRQ 8-15, its output goes to IR2 of the master².

2. The IO APIC ^{[datasheet] [OSDev wiki]}.
   _{Do not confuse the IO APIC with the LAPIC.}
    
   There can be one or multiple IO APICs, all memory mapped at variable (but usually fixed) addresses, each with a variable number of input pins INTINx.
   Usually, one of the IO APIC is wired and configured to emulate the PICs, INTIN0-15 are mapped to IRQ0-15 but this is not a requirement.

3. Message signalled interrupts^{[OSDev forum thread]}
   This is not an interrupt controller (hence it doesn't add up in the count) but it's worth mentioning.
   The PIC was the first generation controller, the IO APIC the second and MSIs are the third.
   They are implemented as writes to specific memory addresses and as such require no controller.
   On an x86 system, a PCI(e) device is configured to do a write into the LAPIC dedicated area³.

The interrupt controllers are configured, along with the LAPIC, to map an IRQ number into a vector number.
The standard configuration for the PIC is

IRQ 0-7  -> INT 08h - 0fh  
IRQ 8-15 -> INT 70h - 77h  

Note that mapping the first IRQs at base 08h was a mistake by IBM (Intel marked the first 32 interrupt vectors as reserved).

Once one knows the IRQ number it is easy to get the INT number, the OS generally can easily make a table for that purpose since it is well known (or can be known with the ACPI tables) how the interrupt controllers are connected to the CPUs.

Associating an IRQ to a device (a process known as interrupt routeing) is very complex because it requires a knowledge of how devices are connected, the ACPI specifications use GSIs to simplify this aspect.

In the end, GSIs (or in ACPI words, system vectors) must be mapped to IRQs, this is done in one-to-one fashion when in PIC mode or by assigning a GSI base (system vector base) to each IO APIC - thereby assigning it all the GSIs from the base to the number of pins minus one.

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With all this in mind, we can finally understand the description of the SCI_INT field:

System vector the SCI interrupt is wired to in 8259 mode. On systems that do not contain the 8259, this field contains the Global System interrupt number of the SCI interrupt.

The text is imprecise in my opinion, Global System interrupt number is just another name for system vector and thus the whole text reduces to "System vector for the SCI interrupt".

The SCI, being a system vector number, it has the nature of a GSI so the number 9 you found is the IRQ 9⁴. By default, IRQ 9 is the INT 71h but any OS that use ACPI surely has remapped the IRQs to a different base and had surely avoided any conflict with the processor exceptions.

Long story short, the number 9 is not an interrupt vector but a system vector (as defined by ACPI).

     GSI        <---->   IRQ     <---->           INT
System vector                                Interrupt vector

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¹the latest at the moment of writing.
² which is configured as it, the 8259A was designed with chaining in mind.
³ which is shared among all LAPIC but can be remapped, especially for non-SMP systems to avoid crossing a QPI link.
⁴ Not strictly true as we know, in APIC mode the GSI 9 can be handled by an IO APIC that doesn't handle ISA IRQs.