Verilog timescale unit constant error(with icarus)

前端 未结 0 1410
清歌不尽
清歌不尽 2021-01-11 14:16

hi i am coding verilog code about uart.

During coding testbench, I can\'t fix this error which is "timescale unit constant (1st digit)"

what can i do

相关标签:
回答
  • 消灭零回复
提交回复
热议问题