How can I assign a “don't care” value to an output in a combinational module in Verilog

Question

Imagine we want to describe a combinational circuit that satisfy the following truth table:

a b | s0 s1 s2 s3
-----------------
0 0 |  1  d  d  d
0 1 |  0  1         


        

Answer 1

When I use Quartus II ver 15.0, assiging "don't care" to output is OK and generated area-efficient circuit.

For example, if I synthesize this code, that :

module test1 (
input wire a,
input wire b,
output reg [3:0] s
);

always @* begin
  case ({a,b})
    2'b00  : s = 4'b1000;
    2'b01  : s = 4'b0100;
    2'b10  : s = 4'b0010;
    2'b11  : s = 4'b0001;
    default: s = 4'b0000; 
  endcase
end
endmodule

Quartus generated a circuit which uses 5 Logic Elements.

However, If I use "don't care" assignment in the code above:

module test1 (
input wire a,
input wire b,
output reg [3:0] s
);

always @* begin
  case ({a,b})
    2'b00  : s = 4'b1xxx;
    2'b01  : s = 4'b01xx;
    2'b10  : s = 4'b001x;
    2'b11  : s = 4'b0001;
    default: s = 4'b0000; 
  endcase
end
endmodule

a circuit which uses only 2 Logic Elements is generated. It's interesting that although the total logic elements are less used, the generated circuit seems to be more complex.

I was wondering whether the generated circuit is correct. So I ran Quartus's simulator with the circuit which uses "don't care". The result is the simplest circuit we want.

Answer 2

I would think that supplying x to an output would do the trick -- "unknown" should do exactly what you want. I believe you can wire it directly as an output, but if that's forbidden, you could generate it by wiring both 1 and 0 to the output.