what is Verilog $signed({1'b0, Level_Config[counter_LRCK-1]})>>>4

Question

sorry my english.

wire signed [15:0] ADC_DATA[11:0]; wire [4:0] Level_Config[11:0]; //32 stage level control ADC_DATA[counter_LRCK-1]*$signed({1\'b0, Level_Confi