VHDL: How to use CLK and RESET in process

Question

I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting

Answer 1

You should only drive a signal from one process. Just put your reset functionality into the counter processes, and it should work. For instance:

process(clk) -- Process for horizontal counter
begin
  if(rising_edge(clk)) then
    if(rst = '1') then
      h_count <= 0;
    else
      if h_count = 799 then
        h_count <= (others => '0');
      else
        h_count <= h_count + 1;
      end if;
    end if;
  end if;
end process;

A few other notes:

As you can see, I've used a synchronous reset in the above snippet. Unless you absolutely need asynchronous resets, use synchronous resets instead. It helps the synthesizer, as there are some special constructs that are not available using asynchronous resets, and it helps prevent problems when your design gets large (and flip-flops suddenly start getting reset at different times due to signal skew).

Also, don't check for anything but edges (or reset) in the initial if statement of a clocked process. For your vertical counter you have a check for h_count = 799. Do the following instead:

process(clk)
begin
  if(rising_edge(clk)) then
    if(h_count = 799) then
    (...)

It's much clearer, and not as prone to errors.

As a last thing, I've changed the clk'event and clk=1 to the more modern way of doing it, rising_edge(clk). It shouldn't make much difference (unless under certain cicrumstances in simulation), but rising_edge has a few extra checks built-in to make sure that you actually have an edge.

Answer 2

You cannot have several drivers for one signal. If you don't have the (clk, reset) process the hcount and vcount signals are each driven by only one process. But when you add the (clk, reset) process it has concurrent drivers.