Is it possible to define a C macro in a makefile?

Question

Is it possible to put the equivalent of #define VAR (in a C program) into a makefile, so that one can control which part of the program should be compiled?

Answer 1

Accordingly to cc manpage on linux

-D name=definition
           The contents of definition are tokenized and processed as if they appeared during translation phase three in a #define directive.  In
           particular, the definition will be truncated by embedded newline characters.

Answer 2

Edit your Makefile to show

CFLAGS=-D VAR1 -D VAR2=*something*

If you are using default rules in the Makefile, this should work automatically. If you do not, and are invoking the C compiler explicitely, just make sure you are writing something along the lines of

$(CC) $(CFLAGS) -c -o $@ $<

Even more cute if the fact the CFLAGS=...above can be used on the command line rather than written in the Makefile (read man(1) manual page); this allows for easy reconfiguration of your compilation parameters at last moment, but the parameters won't be kept.

Best practices include using CPPFLAGS instead of CFLAGS, and using += instead of =; however support for these features are not as universal as the above, and depend on your make system.

Answer 3

Yes.

Most compilers support command line options for specifying #define's. For Visual C++, this is the /D option.