Dividing in Verilog (Coding a Calculator)

Question

 module Project2(clock, reset, w, answer, display);

input clock, reset;
input [3:0]w;

reg [3:0] A0=0,A1=0,A2=0,A3=0;
reg [3:0] B0=0,B1=0,B2=0,B3=0;
reg negA=0, neg