VHDL “expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR” when that is the type I'm giving

Question

library IEEE;

use work.vec9Arr.all; 
use IEEE.STD_LOGIC_1164.all;

entity vector_scalar_multiplier is
port(
    in_a : in vec9arr;
    in_b : in std_logic_vector(15