How does signal assignment work in a process?

Question

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here:

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signal x,y,z : bit;
         


        

Answer 1

I disagree with Ashraf's post. I have made vhdl code myself where variables are wires, and signals are latches. Examples:

signal x,y,clk; process(clk) begin x <= y end process

This creates a synchronous latch, a flip flop.

Any variable which does not assign its value to a signal, but only to other variables, is a perfectly acceptable "wire".

My understanding of the whole subject is this:

A signal assignment inside a process will disregard other signal assignments made in the same process "instantiation". Also, for the same signal, only the last assignment will be taken into account.

About "Ok END OF THE PROCESS: What does it happen?????":

I think that a signal assignment will take place at the fastest possible time the hardware utilization of the process allows. EXCEPTION: Changes within a if(rising_edge(clk)) will take place at the start of the next clock cycle.

Answer 2

Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest).

a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes

Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel

Answer 3

The way it works:

Y changes and the process begins.

X will be assigned to what Y's value currently is, but not until the end of the process

Z will be assigned to not X's old value but not until the end of the process

The process ends so now X and Z will be updated