I\'m trying to compile a simple hello world module following this guide and I\'m confused about what the Makefile is actually doing.
obj-m += hello-1.o
all:
To compile kernel module, the make
command you normally need is in this form:
make -C /lib/modules/3.16.0-70-generic/build M=/home/test/ldd3/hello modules
in which, -C
means switching to another path.
/lib/modules/3.16.0-70-generic/
is the path to the kernel in used, and
/home/test/ldd3/hello
is where the source of your module resides.
what does the M=$(PWD) modules do?
So as I said M=$(PWD)
is simply a shell variable that stores the current path to your kernel module. make
needs to store this as it switches to the kernel build path.
'all and clean' :- If you run 'make' by default it will run "all :". But we can use all and clean with make. it will run only those specific command.
Example :-
'make all' will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules"
'make clean will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean"
3.'uname -r' :- get name and information about current kernel.
Example :- for me, my kernel is "4.6.0-rc1".
Option ‘-C dir’ :- Change to directory dir before reading the makefiles.
Example :- "make -C /lib/modules/$(shell uname -r)/build" will change to "make -C /lib/modules/4.6.0-rc1/build.
Now you want to create your loadable module by using "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules".
Your source code need environment to run. That's why we have to use -C option to change build directory. Which have all needed definition, header file, Macro and etc. Now after changing to build directory you need to tell where is your module present, that's why we are using M=$PWD.