I have a makefile template to compile a single DLL (for a plugin system). The makefile of the user looks like this:
EXTRA_SRCS=file1 file2
include makefile.in
You didn't specify what compiler(s) you are using, but if you have access to gcc/g++ you can use the -MM option.
What I do is create a file with the extension of .d for every .c or .cpp file, and then "include" the .d files. I use something like this in my Makefile:
%.d: %.c
gcc $(INCS) $(CFLAGS) -MM $< -MF $@
%.d: %.cpp
g++ $(INCS) $(CXXFLAGS) -MM $< -MF $@
I then create the dependencies like this:
C_DEPS=$(C_SRCS:.c=.d)
CPP_DEPS=$(CPP_SRCS:.cpp=.d)
DEPS=$(C_DEPS) $(CPP_DEPS)
and this at the bottom of the Makefile:
include $(DEPS)
Is this the kind of behavior you're going for? The beauty of this method is that even if you're using a non-GNU compiler for actual compiling, the GNU compilers do a good job of calculating the dependencies.
Use the "wildcard" function:
$(wildcard *.h)
EDIT: in order to match a specific list, do
$(wildcard $(HEADER_FILES))
There is no need to use $(filter ...), the wildcard function automatically filters files which don't exist.
Does the simple
$(filter $(wildcard *.h),$(HEADER_FILES))
do what you want?