VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

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一整个雨季
一整个雨季 2021-02-09 01:06
  • In verilog, I can assign a string to a vector like:

    wire [39:0] hello;
    assign hello = \"hello\"; 
    
  • In VHDL, I\'m having diffic

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  • 2021-02-09 01:39

    In your example you are trying to assign a string type to a std_logic_vector type. That is simply not allowed. VHDL is strongly typed.

    SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0); ... hello <= "hello";

    If your goal is to convert from hexa to ascii for printing simulation result you can simply do that:

    character'val(to_integer(unsigned(my_std_logic_vector)))

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  • 2021-02-09 01:47

    A small general function is one way to do it, with a suggestion below:

    library ieee;
    use ieee.numeric_std.all;
    ...
    -- String to std_logic_vector convert in 8-bit format using character'pos(c)
    --
    -- Argument(s):
    -- - str: String to convert
    --
    -- Result: std_logic_vector(8 * str'length - 1 downto 0) with left-most
    -- character at MSBs.
    function to_slv(str : string) return std_logic_vector is
      alias str_norm : string(str'length downto 1) is str;
      variable res_v : std_logic_vector(8 * str'length - 1 downto 0);
    begin
      for idx in str_norm'range loop
        res_v(8 * idx - 1 downto 8 * idx - 8) := 
          std_logic_vector(to_unsigned(character'pos(str_norm(idx)), 8));
      end loop;
      return res_v;
    end function;
    
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  • 2021-02-09 01:57

    This one varies little for Morten's answer - it only uses one multiply, it copies the string instead of creating an alias, it uses an additional variable and it returns a standard logic vector with an ascending index range.

    From a package called string_utils:

    library ieee; 
    use ieee.numeric_std.all;
    -- ...
        function to_slv(s: string) return std_logic_vector is 
            constant ss: string(1 to s'length) := s; 
            variable answer: std_logic_vector(1 to 8 * s'length); 
            variable p: integer; 
            variable c: integer; 
        begin 
            for i in ss'range loop
                p := 8 * i;
                c := character'pos(ss(i));
                answer(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); 
            end loop; 
            return answer; 
        end function; 
    

    You could add an argument with a default specifying ascending/descending index range for the return value. You'd only need to provided the argument for the non default.

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