Calculating the effect of the cache on the overall CPI of the processor

Question

How does one calculate the effect of L1 and L2 cache\'s on the overall CPI of the processor given base CPI, miss rate % of L1 and L2 caches and access times of L1, L2, and the m

Answer 1

I think you are not taking into account the Average Number of Memory Accesses per Instruction (AMAPI).

For example, if there are 30% of load/store instructions, this number would be 1.3 (one access to fetch the instruction and 0.3 due to memory access instructions)

So

CPI = BaseCPI + (AMAT - ideal memory access time) x AMAPI

Being AMAT the Average Memory Access Time. For a two-level hierarcchy:

AMAT = L1_hit_latency + L1_miss_rate x (L2_hit_latency + L2_miss_rate x Main_Memory_latency)

Answer 2

Yes, the miss rate of the L2 means the % of misses out of total L2 accesses. Total L2 accesses are the total number of memory accesses * miss rate of the L1.

So, your calculation should be -

CPI = BaseCPI + (% of L1 Miss x L2 Access Time) + ( %L1 miss rate x % L2 miss rate x Memory Access time)  

or more conveniently:

CPI = BaseCPI + (% of L1 Miss x (L2 Access Time + (%L2 miss rate x Memory Access time)))

That's also not very accurate - you didn't specify the rate of memory operations, the above is assuming that every instruction is going to lookup the caches, which is a bit exaggerated. If you have a rate of loads/stores in the program you'll have to factor it in as well.

By the way, in the real world you also need to add the following to the total L2 accesses:

1. L1 writebacks
2. Code reads, if originating from a separate instruction L1
3. HW prefetching

But these are usually ignored in simple calculations as this (and you don't know the % of modified lines, so you can't deduce how many writebacks you'll have anyway).

One more note - it's not really The CPI of the cache, the cache itself doesn't perform instructions or cares about their timing. The proper term would be - The effect of the cache (or any other feature) on the overall CPI of the processor.