How is RAM able to acess any place in memory at O(1) speed

后端 未结 4 1523
遥遥无期
遥遥无期 2021-02-04 21:21

We are taught that the abstraction of the RAM memory is a long array of bytes. And that for the CPU it takes the same amount of time to access any part of it. What is the device

相关标签:
4条回答
  • 2021-02-04 21:41

    What the heck, I might as well make this an answer.

    Yes, in the physical world, memory access cannot be constant time.

    But it cannot even be logarithmic time. The O(log n) circuit you have in mind ultimately involves some sort of binary (or whatever) tree, and you cannot make a binary tree with constant-length wires in a 3D universe.

    Whatever the "bits per unit volume" capacity of your technology is, storing n bits requires a sphere with radius O(n^(1/3)). Since information can only travel at the speed of light, accessing a bit at the other end of the sphere requires time O(n^(1/3)).

    But even this is wrong. If you want to talk about actual limitations of our universe, our physics friends say the absolute maximum number of bits you can store in any sphere is proportional to the sphere's surface area, not its volume. So the actual radius of a minimal sphere containing n bits of information is O(sqrt(n)).

    As I mentioned in my comment, all of this is pretty much moot. The models of computation we generally use to analyze algorithms assume constant-access-time RAM, which is close enough to the truth in practice and allows a fair comparison of competing algorithms. (Although good engineers working on high-performance code are very concerned about locality and the memory hierarchy...)

    0 讨论(0)
  • 2021-02-04 21:42

    The component responsible for dealing with memory accesses is the memory controller. It is used by the CPU to read from and write to memory.

    The access time is constant because memory words are truly layed out in a matrix form (thus, the "byte array" abstraction is very realistic), where you have rows and columns. To fetch a given memory position, the desired memory address is passed on to the controller, which then activates the right column.

    From http://computer.howstuffworks.com/ram1.htm:

    Memory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell.

    So, basically, the answer to your question is: the memory controller figures it out. Of course that, given a memory address, the mapping to column and row must be easy to calculate in a constant time.

    To fully understand this topic, I recommend you to read this guide on how memory works: http://computer.howstuffworks.com/ram.htm

    There are so many concepts to master that it is difficult to explain it all in one answer.

    0 讨论(0)
  • 2021-02-04 21:49

    I've been reading your comments and questions until I answered. I think you are on the right track, but there is some confusion here. The random access in which you are implying doesn't exist in the same way you think it does.

    Reading, writing, and refreshing are done in a continuous cycle. A particular cell in memory is only read or written in a certain interval if a signal is detected to do so in that cycle. There is going to be support circuitry that includes "sense amplifiers to amplify the signal or charge detected on a memory cell."

    Unless I am misunderstanding what you are implying, your confusion is in how easy it is to read/write to a cell. It's different dependent on chip design but there IS a minimum number of cycles it takes to read or write data to a cell.

    These are my sources:

    http://www.doc.ic.ac.uk/~dfg/hardware/HardwareLecture16.pdf
    http://www.electronics.dit.ie/staff/tscarff/memory/dram_cycles.htm
    http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf
    

    To avoid a humungous answer, I left most of the detail out but all three of these will describe the process you are looking for.

    0 讨论(0)
  • 2021-02-04 21:52

    Let's say your RAM has 2^64 cells (places where it is possible to store a single value, let's say 8-bit). Then it needs 64 pins to address every cell with a different number. When at the input pins of your RAM there 'appears' a binary number X the RAM can send the value from cell addressed X to some output pins, and your CPU can get the value from there. In hardware the addressing can be done quite easily, for example by using multiple NAND gates (such 'addressing device' from some logic gates is called a decoder).

    So it is all happening at the hardware-level, this is just direct addressing. If the CPU is able to provide 64 bits to 64 pins of your RAM it can address every single memory cell (as 64 bit is enough to represent any number up to 2^64 -1). The only reason why you do not get the value immediately is a kind of 'propagation time', so time it takes for the signal to go through all the logic gates in the circuit.

    0 讨论(0)
提交回复
热议问题