Makefile: Passing command line arguments to file inside Makefile

Question

Inside my Makfile I have the following,

smktestrun: smktest
    @../projects/test.sh

And I call this using:

Make smktestrun
<         


        

Answer 1

Something like

smktestrun: smktest
        @../projects/test.sh $(TESTARGS)

Then call the Makefile with

$ make smktestrun TESTARGS="-abc"

Answer 2

You could define a variable in Makefile.

smktestrun: smktest
    @../projects/test.sh ${ARG}

Then the command line of make is:

make smktestrun ARG="something"