How to mask bytes in ARM assembly?

前端 未结 5 1003
醉酒成梦
醉酒成梦 2021-02-04 15:53

i have got an 32bit (hexadecimal)word 0xaabbccdd and have to swap the 2. and the 3. byte. in the end it should look like 0xaaccbbdd

how can i \"mask\" the 2nd and the 3r

相关标签:
5条回答
  • 2021-02-04 15:57

    Hmmm, dont know what happened, it submitted my answer before I had really started.

    At first I didnt think I could do it with only two registers but then I decided I could and did. These solutions are register only, no memory (other than the ldr r0,= which you can replace with four instructions). If you use memory and hmmm, two registers you can cut down the number of instructions perhaps, str, bic, bic, ldrb, orr lsl, ldrb, orr lsl. Okay I did it in one instruction fewer but then you need the memory location and the stores and loads cost cycles so same amount of memory and more cycles for me to do it with memory. Someone else may have some good tricks. I think some of the newer cores have an endian swap instruction which would make it even easier.

    .globl midswap
    midswap:
        mov r2,r0,lsl #8      ;@ r2 = BBCCDDAA
        mov r3,r0,lsr #8      ;@ r3 = DDAABBCC (this might drag a sign bit, dont care)
        and r2,r2,#0x00FF0000 ;@ r2 = 00CC0000
        and r3,r3,#0x0000FF00 ;@ r3 = 0000BB00
        bic r0,r0,#0x00FF0000 ;@ r0 = AA00CCDD
        bic r0,r0,#0x0000FF00 ;@ r0 = AA0000DD
        orr r0,r0,r2          ;@ r0 = AACC00DD
        orr r0,r0,r3          ;@ r0 = AACCBBDD
        bx lr ;@ or mov pc,lr for older arm cores
    
    
    .globl tworegs
    tworegs:
        mov r2,r0,ror #8       ;@ r2 = DDAABBCC
        bic r2,r2,#0xFF000000  ;@ r2 = 00AABBCC
        bic r2,r2,#0x00FF0000  ;@ r2 = 0000BBCC
        orr r2,r2,ror #16      ;@ r2 = BBCCBBCC
        bic r2,r2,#0xFF000000  ;@ r2 = 00CCBBCC
        bic r2,r2,#0x000000FF  ;@ r2 = 00CCBB00
        bic r0,r0,#0x00FF0000  ;@ r0 = AA00CCDD
        bic r0,r0,#0x0000FF00  ;@ r0 = AA0000DD
        orr r0,r0,r2           ;@ r0 = AACCBBDD
        bx lr
    
    testfun:
        ldr r0,=0xAABBCCDD
        bl midswap
    
    0 讨论(0)
  • 2021-02-04 16:03

    Back in the day we used to rely heavily on EOR for this kind of trickery.

    You can do it in 4 cycles.

    First off, we need the fact that: A ^ (A^B) = B

    We start with 0xAABBCCDD, and we want 0xAACCBBDD. To get there, we need 0x00EEEE00^0xAABBCCDD, where EE = BB^CC.

    Now, we need a few cycles to build 00EEEE00:

    eor     r1,r0,r0,lsr #8
    and     r1,r1,#0xFF00
    orr     r1,r1,r1,lsl #8
    eor     r0,r0,r1
    

    In c:

    t=x^(x>>8);
    t=t&0xFF00;
    t=t|(t<<8);
    x^=t;
    

    After each line, the result calculated is: starting with: AABBCCDD

    eor  XXXXEEXX
    and  0000EE00
    orr  00EEEE00
    eor  AACCBBDD
    

    This will work on any 32bit ARM core.

    0 讨论(0)
  • 2021-02-04 16:07

    You vould just use pointers to swap two bytes

    static union {
     BYTE   BBuf[4];
     WORD   WWBuf[2];
     DWORD  DWBuf;
    }swap;
    
    unsigned char *a;
    unsigned char *b;
    swap.DWBuf = 0xaabbccdd;
    
    a = &swap.BBuf[1];
    b = &swap.BBuf[2];
    
    *a ^= *b;
    *b ^= *a;
    *a ^= *b;
    

    And now the result is

    swap.DWbuf == 0xaaccbbdd;
    
    0 讨论(0)
  • 2021-02-04 16:09

    That's not a simple task in ARM assembly because you can't easily use 32 bit constants. You have to break up all your operations that mask out bytes to use 8 bit constants each (also these constants can be rotated).

    You mask out byte2 and 3 using the AND instruction and do the shift later. in ARM-assembler you have with most instruction one shift for free, so the shift-into-position and merge with the other bits often end up being a single instruction.

    Here is some untested code that does the middle byte swap (ARMv4, not thumb-instruction set):

            .text
    
    swap_v4:
            AND     R2, R0, #0x00ff0000     @ R2=0x00BB0000 get byte 2
            AND     R3, R0, #0x0000ff00     @ R3=0x0000CC00 get byte 1
            BIC     R0, R0, #0x00ff0000     @ R0=0xAA00CCDD clear byte 2
            BIC     R0, R0, #0x0000ff00     @ R0=0xAA0000DD clear byte 1
            ORR     R0, R2, LSR #8          @ R0=0xAA00BBDD merge and shift byte 2
            ORR     R0, R3, LSL #8          @ R0=0xAACCBBDD merge and shift byte 1
            B       LR
    

    That translate line by line into the following c-code:

    int swap (int R0)
    {
      int R2,R3;
      R2 = R0 & 0x00ff0000;
      R3 = R0 & 0x0000ff00;
      R0 = R0 & 0xff00ffff;
      R0 = R0 & 0xffff00ff;
      R0 |= (R2>>8);
      R0 |= (R3<<8);
      return R0;
    }
    

    You'll see - lots of lines for such a simple task. Not even the ARMv6 architecture helps here much.


    EDIT: ARMv6 version (also untested, but two instructions shorter)

    swap_v6:
            @ bits in R0: aabbccdd
            ROR     R0, R0, #8              @ r0 = ddaabbcc
            REV     R1, R0                  @ r1 = ccbbaadd
            PKHTB   R0, R0, R1              @ r0 = ddaaccbb
            ROR     R0, R0, #24             @ r0 = aaccbbdd
            BX      LR
    
    0 讨论(0)
  • 2021-02-04 16:10

    Can you use BFI and UBFX they will make your job easier

    0 讨论(0)
提交回复
热议问题