Is initialization necessary?

Question

In VHDL, is initialization necessary when creating a signal or a vector? What happens if one forgets to initialize a signal or integer value?

Answer 1

In simulation, if you do not set an initial value, each element of your vector will get the default value (this is defined by the VHDL language specification). For enum types, this is the first element defined in the enumeration type: booleans will be false, std_logic will be 'U' (undefined). Note that 'U' has no meaning in electrical circuits. It is merely a hint for the verification engineer that you don't know which value the flip-flop has at power-on.

After synthesis: FPGA synthesizers will use the initial value that you set as the "power on" value of the flip-flops and memories if the target technology supports this! If the technology does not support a forced initial value (and for ASICs), the initial value at power-on is not known. It could be 1 or 0. (See for example: http://quartushelp.altera.com/11.0/mergedProjects/hdl/vhdl/vhdl_pro_power_up_state.htm)

Two possible styles:

1. Choose an explicit initial value, with or without explicit reset circuits (usually for modern FPGAs)
2. Set 'U' as initial value, and have a proper reset circuit to force a known reset value

If you go with the first choice, be sure to check if your target technology supports this style!

Answer 2

It is not strictly necessary in VHDL, just like it is not necessary in C/C++, but a similar result can occur. Without initializing a signal or vector of signals, a simulator will typically simulate that it is in an unknown state (assuming you are using std_logic signals). However, a synthesis engine will pick one or the other as an initial value since when an FPGA is programmed all memory elements will be initialized one way or another (i.e. they are not initialized to an unknown state).

Some people will not initialize a signal on declaration, but will instead use their circuit to initialize the memory element (e.g. create reset logic to initialize the memory element). Other will initialize the memory element when it is declared. These are design decisions which have their own tradeoffs.

Answer 3

In simulation, everything in VHDL is initialised at the start to the "left-most" element of the range which represents them.

So, std_logic will get 'U', boolean will get false, integer will get a big negative number. Any enumerated types you've defined yourself will init to their first member. etc.

You can override this with an explicit initialisation:

variable i : integer := 0;

the simulator will then use your initialisation.

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When it comes to synthesising your code, in an ASIC, explicit initialisations are ignored (there's no silicon to support them!), and everything initialises unpredictably. So you have a reset pin and explicit code which assigns the value you want when that pin is asserted.

When you target an FPGA and don't explicitly initialise, most of the time things will initialise to something 'like zero', but you can't rely on it (sometimes inverters are pushed around and things look like they've inited to 'one'). So you have a reset pin and explicit code which assigns the value you want when that pin is asserted.

Some synthesisers (XST at least) will support explicit initialisations and pass them into the netlist so that you can rely on them. In this case you can still have a reset signal - which can do something different so a particular flipflop could initialise to one value and reset to another!