Consider the following problem. You have a bit-string that represents the current scheduled slave in one-hot encoding. For example, \"00000100\" (with the leftmost bit being #7
Complete parametrizable arbiter implementation that can be configured for round-robin or priority arbitration:
https://github.com/alexforencich/verilog-axis/blob/master/rtl/arbiter.v
This design uses a pair of priority encoders to select the next output in the sequence. The priority encoders used are implemented efficiently as trees.