Reverse bit order on VHDL

Question

I\'m having trouble doing something like

b(0 to 7) <= a(7 downto 0)

when I compile it with ghdl, I have an order error. The only way I have

Answer 1

Really inverting:

for i in 0 to intermediate_data'left loop

  inverted_vector(i) <= intermediate_data(intermediate_data'left - i);

end loop;