Reverse bit order on VHDL

Question

I\'m having trouble doing something like

b(0 to 7) <= a(7 downto 0)

when I compile it with ghdl, I have an order error. The only way I have

Answer 1

The question asks how to deal specifically with b(0 to 7) <= a(7 down 0). I don't know of the reasons, but sometimes this assignment works for me (assigns things from left to right regardless of the slicing) and sometimes this assignment throws compiler errors (mismatched slicing or something).

Fortunately you do not need to use a function to handle mismatched slicing. If you are getting compiler errors for this specific problem you can use a generate loop to assign a to b.

for i in a'range generate
   b(i) <= a(i)  
   --when i is 0, you assign a's right-most bit to b's left-most bit
end generate;

It does basically the same unrolled assignment as in your example, just tight and scale-able.

I've also used this pattern when I have mismatched slicing on the right side of the assignment. For example:

signal a : std_logic_vector(0 to 7);
signal b : std_logic_vector(7 downto 0);
signal c : std_logic_vector(0 to 7);

...

for i in a'range generate
   c(i) <= a(i) xor b(i);
end generate;

Which is equivalent to:

c(0) <= a(0) xor b(0);
c(1) <= a(1) xor b(1);
c(2) <= a(2) xor b(2);
c(3) <= a(3) xor b(3);
c(4) <= a(4) xor b(4);
c(5) <= a(5) xor b(5);
c(6) <= a(6) xor b(6);
c(7) <= a(7) xor b(7);