Reverse bit order on VHDL

Question

I\'m having trouble doing something like

b(0 to 7) <= a(7 downto 0)

when I compile it with ghdl, I have an order error. The only way I have

Answer 1

That's not allowed - VHDL is so strongly typed that if you want to reverse bit orders, you have to do it explicitly.

The standard solution is to use a function (I didn't write this - Jonathan Bromley did):

function reverse_any_vector (a: in std_logic_vector)
return std_logic_vector is
  variable result: std_logic_vector(a'RANGE);
  alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
  for i in aa'RANGE loop
    result(i) := aa(i);
  end loop;
  return result;
end; -- function reverse_any_vector