I have a legacy firmware application that requires new functionality. The size of the application was already near the limited flash capacity of the device and the few new funct
The above answers claim "Turning on compiler optimization [reduced the code size]". Given all the documentation and experience I have had in embedded systems TI DSP programming, I know for a fact that turning on optimization will INCREASE your code size ( for TI DSP chip ) !
Let me explain:
The TI TMSCx6416 DSP has 9 compiler flags that will affect your code size.
For my compiler, when you turn on optimization level three the documentation states:
What is software pipelining?
That is where the compiler will do things in assembly that make the for loops execute significantly faster ( up to a couple times faster ) but at the cost of greater code size. I suggest reading about software pipelining at wikipedia ( look for loop unrolling, prolog, and epilog ).
So check your documentation to make sure the optimization isn't making your code larger.
Another suggestion is to look for compiler flags that relate to code size. If you have code size compiler flags, make sure to crank up them up to the highest setting. Usually compiling for code size means your code will execute slower... but you may have to do that.