How to Synthesize While Loop in Verilog?

Question

I have tried to design a Booth multiplier and it runs well in all compilers including:

Modelsim,Verilogger Extreame,Aldec Active Hdl & Xilinx\'s Isim......<

Answer 1

While loops tend to imply something dynamic, like checking a condition. This is not a good use of verilog intended for synthesis. For loops which can be statically unrolled are more commonly used to shorten the written code.

If you need some thing more dynamic a dedicated state machine should be written.

To answer some of the questions raised in the comments:

Combinatorial logic uses assign or is contained in always @* this is continuously evaluated and all runs in parallel think AND, OR, NOR gates.

Sequential logic will be contained in an always @( posedge clk ) this is executed on every positive edge of the clock. The registers or memory elements used inside of this typically represent Flip-Flops.