How to Synthesize While Loop in Verilog?

Question

I have tried to design a Booth multiplier and it runs well in all compilers including:

Modelsim,Verilogger Extreame,Aldec Active Hdl & Xilinx\'s Isim......<

Answer 1

This is poorly written code.You have written it like a computer program. Verilog is a Hardware Description Language - not a programming language. In your case, synthesizer is trying to replicate logic inside the while loop in the case statement.

• Design the hardware on a piece of paper before translating it to HDL
• Identify the combinational and sequential logic in the design before coding.
• Think what logic will synthesizer use to realize the logic you have written.