On x86-16 bit:
int a; // two bytes
struct{
char b; // One byte.
struct{ // Struct itself is aligned to the size of pointer
short *c[20]; // pointers may be 2 or 4 bytes depending on compile mode.
char d; // one byte
}e;
}f;
double g; // 8 bytes aligned to 8 bytes.
char *h; // 2 or 4 bytes.
On x86-32 bit:
int a; // four bytes.
struct{
char b; // one byte.
struct{ // struct padding to size of pointer.
short *c[20]; // pointers are 4 bytes.
char d; // one byte.
}e;
}f;
double g; // 8 bytes, aligned to 8 bytes.
char *h; // 4 bytes.
On x86-64:
int a; // 4 bytes.
struct{
char b; // One byte.
struct{ // struct aligned to size of pointer
short *c[20]; // Pointers are 4 or 8 bytes (typically 8)
char d; // One byte.
}e;
}f;
double g; // 8 bytes. Aligned to 8 bytes.
char *h; // 4 or 8 byte pointer, aligned to size of pointer.
In some other architecture, this is perfectly valid:
int a; // 8 bytes
struct{
char b; // 4 bytes.
struct{ // Struct is not aligned to anything.
short *c[20]; // Pointers are 8 bytes.
char d; // 4 bytes
}e;
}f;
double g; // 12 bytes, aligned to 4 bytes.
char *h; // pointers are 8 bytes.
I'll let you do the math for each example to calculate what the actual address is. But like everyone else has said, the layout is entirely up to the compiler, and is not possible to determine without understanding the rules of the particular compiler/architecture of the processor.
