ACTIV HDL - VHDL-“Signal cannot be synthesized, bad synchronous description”

Question

I have a error while Synthesize this code in Xillinx. This error is:

\"Signal Z_1 cannot be synthesized, bad synchronous description\"

Answer 1

You have an if clause that contains a check for reset condition, then two separate gated clock conditions and then an else clause. I don't think there's any tool that will synthesize this, because it's highly unlikely you actually want what you describe and it'd be reasonably hard to put in hardware anyway. You need to read more about the basics of HDL and synchronous design.

Think about it this way: If you read the code you wrote from top to bottom, line for line, as the compiler does, how would you actually go about building hardware that does what you described? How do you build a piece of hardware that does one thing on one clock, another thing on another clock and a third thing when no clock at all is applied? How do you implement this in your FPGAs LUTs?

In short, to get your code to work, you need to get rid of the else clause, it does nothing anyway and synthesizers generally don't like else or elsif-clauses alongside a clocking conditional(if rising_egde(clk) or if clk'event and clk = '1'). The condition of C should be checked in a separate if clause inside your main clocked statement. Also, get rid of the check for rst = '0' in the elsif clause. You already checked for rst = '1' in the if statement and a bit signal can only be '1' or '0'.

Synthesizable code would look like this:

process (clk, rst)
   if rst = '1' then
       -- your reset condition
   elsif clk'event and clk = '1' then -- if you use a bit type clk, otherwise use elsif rising_edge(clk) then
       if signal = condition then
          -- whatever you need doing
       else
          -- whatever you need doing
       end if;
   end if;
end process;