VHDL Synthesis - FF/Latch Constant Value

Question

I am trying to synthesize a vhdl module I have written.

The code is below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library         


        

Answer 1

It is better to set the expected range of your integers; that way synthesis will generate them the correct size in the first place, rather than 32 bits and then emit hundreds of "trimming" warnings.

Either of

variable clkCount : integer range 0 to totalBitWidth := 0;

can it ever be negative? no? then better...

variable clkCount : natural range 0 to totalBitWidth := 0;
variable Sum      : natural range 0 to majorityValue := 0;

or USE the type system.

For example, if there is a relationship between totalBitWidth and majorityValue, then express it directly instead of making them independent : less to track and get wrong when you change totalBitWidth. (I am guessing at the intended relationship below)

type counttype is new integer range 0 to totalBitWidth;
subtype sumtype is counttype range 0 to totalBitWidth / 2 + 1;

    variable clkCount : counttype := 0;
    variable Sum      : sumtype   := 0;