Verilog error: not a valid l-value

Question

I\'m trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code:

output reg[3:0]x;                                


        

Answer 1

Your using the assign incorrectly. That can be used outside of a always process, but not inside of one.
Also, the type wire, is required for an assign

wire [3:0] x;
assign x = 4'b1111;

Inside the always process, remove the assign statement and just say

reg [3:0] x;  // Note that this is assigned as a reg now
 always @* begin
    if(blah) begin 
       x = 4'b1111;
    end else begin
       x = opcode;
    end
 end